CTU FEE Moodle
VLSI System Design
B232 - Summer 23/24
This is a grouped Moodle course. It consists of several separate courses that share learning materials, assignments, tests etc. Below you can see information about the individual courses that make up this Moodle course.
VLSI System Design - A0M34NSV
Main course
| Credits | 4 |
| Semesters | Winter |
| Completion | Assessment + Examination |
| Language of teaching | Czech |
| Extent of teaching | 2P+2L |
Annotation
Introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems. Structure and design of digital and analogue integrated circuit subsystems. Integrated system description and synthesis using cell libraries and IP cores. Synchronization, power consumption and parasitics reduction issues. Testing and reliability of integrated systems. In seminars and labs, the hardware description language VHDL will be explained and used for practical design, synthesis and testing of a system on chip.
Study targets
The aim of the subject is introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems.
Course outlines
1. VLSI system design, principles and hierarchy. Design methodology.
2. Levels of system description. Hardware description languages for behavioral and RTL description.
3. Code structure, semantics and syntax.
4. Assignments of hardware function, concurrent and sequential domains and their interpretation.
5. Hierarchy, design of parametric models and libraries. System description in SystemVerilog and SystemC.
6. Hardware platforms, target architectures, programmable and reconfigurable systems.
7. System on chip design, design re-use, Intellectual Property (IP) cores.
8. Behavioral synthesis: RTL model, algorithms and procedures. Logical synthesis: methods and constraints. Synthesis of topology. Control of system synthesis.
9. Models of integrated systems and structures, standards.
10. Testing and reliability. Fault models and methods of localization.
11. Verification flow and strategies.
12. Verification tools: simulators and models.
13. Test design and analysis: stimuli, responses and testbenches (design and architecture).
14. VLSI system project management, risk minimization, documentation, reviewing.
2. Levels of system description. Hardware description languages for behavioral and RTL description.
3. Code structure, semantics and syntax.
4. Assignments of hardware function, concurrent and sequential domains and their interpretation.
5. Hierarchy, design of parametric models and libraries. System description in SystemVerilog and SystemC.
6. Hardware platforms, target architectures, programmable and reconfigurable systems.
7. System on chip design, design re-use, Intellectual Property (IP) cores.
8. Behavioral synthesis: RTL model, algorithms and procedures. Logical synthesis: methods and constraints. Synthesis of topology. Control of system synthesis.
9. Models of integrated systems and structures, standards.
10. Testing and reliability. Fault models and methods of localization.
11. Verification flow and strategies.
12. Verification tools: simulators and models.
13. Test design and analysis: stimuli, responses and testbenches (design and architecture).
14. VLSI system project management, risk minimization, documentation, reviewing.
Exercises outlines
1. Design system ISE: introduction into integrated system design - entry, synthesis, implementation.
2. Design system ISE: functional, logical and timing analysis. Digital system model in HDL
3.HDL - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.
4. HDL - hierarchical design and verification models (testbenches).
5. HDL - state automata description and design of complex sequential systems.
6. State automata description in the StateCad environment, end of model project.
7. Migration of model design into different architectures, design reuse.
8. IP core libraries, design using IP core generators.
9. Floor planning and timing analysis, design of architecture specific blocks.
10. Description of course works, used IP modules, test.
11. Practical design of integrated system based on FPGA or SoC.
12. Practical design of integrated system based on FPGA or SoC.
13. Practical design of integrated system based on FPGA or SoC.
14. Presentation of course works, correction test, account.
2. Design system ISE: functional, logical and timing analysis. Digital system model in HDL
3.HDL - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.
4. HDL - hierarchical design and verification models (testbenches).
5. HDL - state automata description and design of complex sequential systems.
6. State automata description in the StateCad environment, end of model project.
7. Migration of model design into different architectures, design reuse.
8. IP core libraries, design using IP core generators.
9. Floor planning and timing analysis, design of architecture specific blocks.
10. Description of course works, used IP modules, test.
11. Practical design of integrated system based on FPGA or SoC.
12. Practical design of integrated system based on FPGA or SoC.
13. Practical design of integrated system based on FPGA or SoC.
14. Presentation of course works, correction test, account.
Literature
1.P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008
2. P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley, 2006
3. P.K.Lala, Principles of Modern Digital Design, Wiley, 2006
2. P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley, 2006
3. P.K.Lala, Principles of Modern Digital Design, Wiley, 2006
Requirements
Successful presentation of semestral project and pass in the final test.
VLSI System Design - B2M34NSV
| Credits | 6 |
| Semesters | Winter |
| Completion | Assessment + Examination |
| Language of teaching | Czech |
| Extent of teaching | 2P+2L |
Annotation
Introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems. Structure and design of digital and analogue integrated circuit subsystems. Integrated system description and synthesis using cell libraries and IP cores. Synchronization, power consumption and parasitics reduction issues. Testing and reliability of integrated systems. In seminars and labs, the hardware description language VHDL will be explained and used for practical design, synthesis and testing of a system on chip.
Study targets
The aim of the subject is introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems.
Course outlines
1. VLSI system design, principles and hierarchy. Design methodology.
2. Levels of system description. Hardware description languages for behavioral and RTL description.
3. Code structure, semantics and syntax.
4. Assignments of hardware function, concurrent and sequential domains and their interpretation.
5. Hierarchy, design of parametric models and libraries. System description in SystemVerilog and SystemC.
6. Hardware platforms, target architectures, programmable and reconfigurable systems.
7. System on chip design, design re-use, Intellectual Property (IP) cores.
8. Behavioral synthesis: RTL model, algorithms and procedures. Logical synthesis: methods and constraints. Synthesis of topology. Control of system synthesis.
9. Models of integrated systems and structures, standards.
10. Testing and reliability. Fault models and methods of localization.
11. Verification flow and strategies.
12. Verification tools: simulators and models.
13. Test design and analysis: stimuli, responses and testbenches (design and architecture).
14. VLSI system project management, risk minimization, documentation, reviewing.
2. Levels of system description. Hardware description languages for behavioral and RTL description.
3. Code structure, semantics and syntax.
4. Assignments of hardware function, concurrent and sequential domains and their interpretation.
5. Hierarchy, design of parametric models and libraries. System description in SystemVerilog and SystemC.
6. Hardware platforms, target architectures, programmable and reconfigurable systems.
7. System on chip design, design re-use, Intellectual Property (IP) cores.
8. Behavioral synthesis: RTL model, algorithms and procedures. Logical synthesis: methods and constraints. Synthesis of topology. Control of system synthesis.
9. Models of integrated systems and structures, standards.
10. Testing and reliability. Fault models and methods of localization.
11. Verification flow and strategies.
12. Verification tools: simulators and models.
13. Test design and analysis: stimuli, responses and testbenches (design and architecture).
14. VLSI system project management, risk minimization, documentation, reviewing.
Exercises outlines
1. Design system ISE: introduction into integrated system design - entry, synthesis, implementation.
2. Design system ISE: functional, logical and timing analysis. Digital system model in HDL
3.HDL - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.
4. HDL - hierarchical design and verification models (testbenches).
5. HDL - state automata description and design of complex sequential systems.
6. State automata description in the StateCad environment, end of model project.
7. Migration of model design into different architectures, design reuse.
8. IP core libraries, design using IP core generators.
9. Floor planning and timing analysis, design of architecture specific blocks.
10. Description of course works, used IP modules, test.
11. Practical design of integrated system based on FPGA or SoC.
12. Practical design of integrated system based on FPGA or SoC.
13. Practical design of integrated system based on FPGA or SoC.
14. Presentation of course works, correction test, account.
2. Design system ISE: functional, logical and timing analysis. Digital system model in HDL
3.HDL - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.
4. HDL - hierarchical design and verification models (testbenches).
5. HDL - state automata description and design of complex sequential systems.
6. State automata description in the StateCad environment, end of model project.
7. Migration of model design into different architectures, design reuse.
8. IP core libraries, design using IP core generators.
9. Floor planning and timing analysis, design of architecture specific blocks.
10. Description of course works, used IP modules, test.
11. Practical design of integrated system based on FPGA or SoC.
12. Practical design of integrated system based on FPGA or SoC.
13. Practical design of integrated system based on FPGA or SoC.
14. Presentation of course works, correction test, account.
Literature
[1] Wayne Wolf : "Modern VLSI Design: System-on-Chip Design", Prentice-Hall, 2002
[2] Samiha Mourad, Yervant Zorian: "Principles of Testing Electronic Systems", John Wiley, 20002
[3] Bruce Wile, John C. Goss, Wolfgang Roesner: "Comprehensive Functional Verification", Elsevier, 2005
[4] P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008
[5] P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley, 2006
[6] P.K.Lala, Principles of Modern Digital Design, Wiley, 2006
[2] Samiha Mourad, Yervant Zorian: "Principles of Testing Electronic Systems", John Wiley, 20002
[3] Bruce Wile, John C. Goss, Wolfgang Roesner: "Comprehensive Functional Verification", Elsevier, 2005
[4] P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008
[5] P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley, 2006
[6] P.K.Lala, Principles of Modern Digital Design, Wiley, 2006
Requirements
Successful presentation of semestral project and pass in the final test.