CTU FEE Moodle
Logic systems and processors
B241 - Winter 2024/2025
Logic systems and processors - B0B35LSP
| Credits | 6 |
| Semesters | Summer |
| Completion | Assessment + Examination |
| Language of teaching | Czech |
| Extent of teaching | 2P+2L |
Annotation
The course introduces computing resources' basic hardware structures, design, and architecture. It provides an overview of the possibilities of performing data operations at the hardware level and designing embedded processor systems with peripherals on modern FPGA programmable logic circuits, which are increasingly widely used today.
Students will learn their description in VHDL, from logic to more complex sequential circuits to practical finite state machine (FSM) designs. They will also master the correct design procedure using circuit simulation. Practical problems are solved using development boards that hundreds of leading universities worldwide also use.
The course ends with RISC-V processor structure, cache, and pipeline processing.
[last updated January 2024]
Students will learn their description in VHDL, from logic to more complex sequential circuits to practical finite state machine (FSM) designs. They will also master the correct design procedure using circuit simulation. Practical problems are solved using development boards that hundreds of leading universities worldwide also use.
The course ends with RISC-V processor structure, cache, and pipeline processing.
[last updated January 2024]
Study targets
Introduction into computers systems and basic constructions of computers peripherials.
Course outlines
1. Introduction. The logical cube and equations of logical functions from the Karnaugh maps.
2. De Morgan's theorem and its application. Shannon's expansion. Basic building blocks and structure of FPGA circuits.
3. From C to VHDL: basic notation, number conversion, and multiplexer usage.
4. Examples of the use of concurrent statements. Introduction to the 2nd practice problem.
5. Sequential domain of VHDL.
6. Gate delays. Gambling in combinational circuits and the need to eliminate them with synchronous circuits. Latches and synchronous per rising edge. Their usage in VHDL.
7. Basic synchronous circuits with DFF, feelings.
8. Shift registers and examples of their use.
9. From counters up down through controllers to general Finite State Machine (FSM) of Moore type.
10. Communication between FSMs, from FSM to processor controllers.
11. The structure of the RISC V processor, its basic 32I version, and the instruction flow.
12. The processor memory system: the cache.
13. Memory paging. Instruction pipelining, data hazards, and branch predictors.
14. Advanced FPGA design topics - soft-core processors.
[last updated January 2024]
2. De Morgan's theorem and its application. Shannon's expansion. Basic building blocks and structure of FPGA circuits.
3. From C to VHDL: basic notation, number conversion, and multiplexer usage.
4. Examples of the use of concurrent statements. Introduction to the 2nd practice problem.
5. Sequential domain of VHDL.
6. Gate delays. Gambling in combinational circuits and the need to eliminate them with synchronous circuits. Latches and synchronous per rising edge. Their usage in VHDL.
7. Basic synchronous circuits with DFF, feelings.
8. Shift registers and examples of their use.
9. From counters up down through controllers to general Finite State Machine (FSM) of Moore type.
10. Communication between FSMs, from FSM to processor controllers.
11. The structure of the RISC V processor, its basic 32I version, and the instruction flow.
12. The processor memory system: the cache.
13. Memory paging. Instruction pipelining, data hazards, and branch predictors.
14. Advanced FPGA design topics - soft-core processors.
[last updated January 2024]
Exercises outlines
None
Literature
Šusta R.: Binární prerekvizita (29 stran)
Šusta R.: Logické obvody na FPGA (135 stran)
Šusta R.: Uvod do VHDL I. - souběžné příkazy - (96 stran)
Šusta R.: Úvod do VHDL II. - sekvenční příkazy - (70 stran) - dosud nedokončená verze beta 0.51 z 6.6.2023.
* Všechny učebnice jsou dostupné v PDF verzi na veřejné stránce předmětu:
https://dcenet.fel.cvut.cz/edu/fpga/navody.aspx
Šusta R.: Logické obvody na FPGA (135 stran)
Šusta R.: Uvod do VHDL I. - souběžné příkazy - (96 stran)
Šusta R.: Úvod do VHDL II. - sekvenční příkazy - (70 stran) - dosud nedokončená verze beta 0.51 z 6.6.2023.
* Všechny učebnice jsou dostupné v PDF verzi na veřejné stránce předmětu:
https://dcenet.fel.cvut.cz/edu/fpga/navody.aspx
Requirements
Boolean algebra, logic circuits