BE5B35LSP - Logic systems and processors - B181

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• BE5B35LSP - Logic systems and processors
  

  BE5B35LSP - Logic systems and processors

  The course is an introduction to basic hardware structures of computing resources, their design, and architecture. It provides an overview of the implementation of data operations at hardware and the creation of embedded processor systems with peripherals on advance programmable logic FPGAs.

  The course requires basic knowledge of logic functions and binary numbers presented in APOLOS prerequisite, see http://dcenet.felk.cvut.cz/edu/fpga/doc/Apolos_V11_eng.pdf

  • News Fórum
  • Important links

    • The submission of tasks  https://dcenet.felk.cvut.cz/fpga/
    • Software installations and study materials:  http://dcenet.felk.cvut.cz/edu/fpga/Default_en.aspx
  • The description of your 1st task with solved example - 15 points - November 15th, 2018, is the dead line Soubor
  • Credits and exam

    To obtain credit from practical exercises, you must solve two tasks assigned to your and obtain from them the sum greater or equal to 50 points.

    To pass the exam, you must get at least 30 points (the half) from written test. The points from practical exercises will be added to these points. If you obtain the sum greater then 100 points you successfully pass the course. The value of your points will determine your grade.

    • 90-99 is E,
    • 100-109 is D
    • 110-119 is C
    • 120-129 is B
    • 130 and above is A
  • 3rd Task Soubor
  • Sample of Written Exam Test - V1.1 - corrected swapped result Q3-f1 Soubor
• Week 1
  

  Week 1

  Lecture - Logic functions

  Practical exercises: Introduction

  • 1st lecture Soubor
• Week 2
  

  Week 2

  Lecture: Shannon expansion, VHDL

  Practical exercises: Project for DE2 board

  • 2nd lecture Soubor
  • Quartus task from Seminary Soubor
• Week 3
  

  Week 3

  Lecture: VHDL concurrent constructions compiled by multiplexer

  Practical exercises: Advance wor with Quartus block diagrams

  • Seminary 1 Soubor
  • 3rd lecture V1.1 - corrected slide 57 Soubor
• Week 4
  

  Week 4

  Lecture: Priority task and VHDL process

  • 4th lecture Soubor
  • Quartus source codes Soubor
  • PatMat -Quartus Soubor
• Week 5
  

  Week 5

  Lecture: RS-latch, Master-Slave flip-flop, flip-flops in VHDL

  • 5th lecture - V11 - added notes to incomplete assignments Soubor
  • Animation of Master-Slave flip-flop Soubor
• Week 6
  

  Week 6

  Lecture:  VHDL registers,  SRAM Memories, Ripple effect in circuits.

  • 6th lecture Soubor
• Week 7
  

  Week 7

  Adders, counters. Combinational hazards and sequential circuits in VHDL. Metastability

  • Slides from lecture Soubor
• Week 8
  

  Week 8

  Finite state machines and control units

  • Slides from lecture Soubor
• Week 9
  

  Week 9

  Exceptionally, the lecture will be held on Thursday, December 6th, at 17:15 in room KN-E-23.

  Processor NIOS, our own processor 42. Phase lock loops.

  • Slides from the lecture Soubor
  • Selected NIOS Instructions Soubor
  • Quartus source code of Processor 42 Soubor
  • Altera: NIOS instruction set reference Soubor
• Week 10
  

  Week 10

  Shift registers and their usage - random generators and CRC codes, Microprogram. Asynchronous bus. 

  • Slides from the lecture Soubor
  • 10th seminary Soubor
  • Nios program for practical exercises Soubor
• Week 11
  

  Week 11

  Integer arithmetics. Integral equations in VHDL. Interconnections on chips. Avalon bus. How to write a professional testbench.

  • Slides from the lecture Soubor
  • Nios VGA Quartus project Soubor
  • Quartus Bin2Gray with the professional testbench Soubor
• Week 12
  

  Week 12

  Nondeterministic automata, finite acceptors, BDD, fix-point arithmetic
• Week 13
  

  Week 13
• Week 14
  

  Week 14